The invention relates generally to the field of information storage, more specifically to hard disk drives and in particular to preamplifier circuits.
U.S. Pat. No. 5,831,888 entitled xe2x80x9cAutomatic Gain Control Circuitxe2x80x9d and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage. Hard disk drives (HDD) are one type of disk storage that are particularly used in personal computers today. The HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servo controller, a memory and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus. The following U.S. Patents describe various aspects of HDD devices:
Prior art FIG. 1 illustrates a disk/head assembly 12 and a preamplifier 14. The preamplifier 14 handles both read functions and write functions. Not illustrated in FIG. 1, for clarity, is the Magentoresistive (MR) head. The unshown MR head works through magnetic media and it has both functions, read and write, with a different portion of the head performing each function. The write function portion of the MR head is inductive and the read function portion of the head acts as a magnetic resistive element. A write occurs through an inductive element to the magnetic media disk assembly 12 and a read occurs by sensing the magnetic shifts in the disk assembly 12 by using the resistive read element. The preamplifier 14 connects to the unshown MR head.
Prior art FIG. 2 illustrates a portion of the read channel of preamplifier 14 of FIG. 1. The resistive portion of the unshown MR head is represented by the resistors Rmr 1-Rmr 6. An initial amplification stage 18 of preamplifier 14 connects to the resistive portion Rmr of the MR head. Later gain stages 20 of preamplifier 14 are connected to the outputs of initial amplification stage 18 at nodes NA and MB. The read path outputs flow from the later gain stages 20. The read channel inputs flow into preamplifier 14 from a head select logic stage. In typical mass storage devices of the HDD type, the preamplifier 14 may have as many as 1 to 8 channels. Transistor SW1 represents the read channel input enabling MOS transistor for head 1 of the 6 heads illustrated in FIG. 2. The other enabling MOS transistors for heads 2-6 are unillustrated for clarity. In the operational example explained below, since read head 1 is illustrated as the selected head, the input NPN transistors Q2-Q6 for the other heads are illustrated in the off condition with their bases being connected to the integrated circuit ground.
The architecture of initial amplification stage 18 of preamplifier 14 is constructed as that of a single ended amplifier as opposed to a differential amplifier; the single ended amplifier uses only one transistor Q11 to set the voltage on the load side of later gain stage 20. (As is known to one of ordinary skill in the art of amplifier design, a differential amplifier uses two transistors to establish the voltages on nodes N and M, one transistor for node N and one transistor on node M.) On one side of the single ended amplifier, the bias current Ib travels through the load resistor R1 and through the collector of transistor Q11 to set the voltage on node M. On the other side of the single ended amplifier, the bias current Ib/xe2x88x9d travels through the scaling resistor xe2x88x9dR1 to set the voltage on node N. (The reference character xe2x88x9d represents the scale factor for the resistor. In this example, the scale factor is 20 and so the scaling resistor is illustrated as 20R1.) In hard disk drives, because of linearity problems during a read operation, the voltage on the read head (represented by VRmr) is biased up to a certain level, which is typically around 0.2 to 0.5 volts. This bias voltage VRmr is established through a feedback loop created by transconductance amplifier 22 across nodes M and N whose output is connected to the base of transistor Q11 through MOS switch SW1. This, in essence, creates a pseudo-balanced output on the reader load resistors such as would exist if a differential amplifier were used in the initial amplification stage.
In operation of prior art FIG. 2, when head 1 is selected, NPN bipolar transistors Q11 and Q1 are on. Together with the load resistor R1, they form a cascode amplifier. A cascode amplifier is a high bandwidth amplifier. The transistor Q1 is a common base amplifier and the transistor Q11 acts as a common base amplifier. As the magnetic resistive head moves over data, the head resistance Rmr varies. This can be modeled by an alternating current ac signal in series with the Rrnr resistor. The transistors Q1 and Q11 amplify this signal. The ac signal goes to the load resistor R1 and then to the base of emitter follower transistor Q8. Then, the signal goes to the node MB input of latter gain stage 20 that is a differential amplifier. The other input of the amplifier 20 is node NA that should be at a dc bias voltage equal to the voltage on the load resistor R1 node MB. The node NA constant voltage side of the later gain stage amplifier 20 should not have an alternating current signal on it. The reference side of single ended initial amplification stage 18 consists of transistors Qb, Q21 and the scaling resistor 20R1. This supplies a current Ib/xe2x88x9d through the scaling resistor 20R1, which provides a voltage at node N. The transconductance amplifier 22 forms a feedback loop with the cascode amplifier Q1 and Q11. The purpose of the loop is to make sure that node M dc voltage on the signal side of the load resistor R1 is the same as the dc voltage on node N. If the dc voltage on node M and node N are the same, the input voltage on differential amplifier 20 at nodes NA. and nodes MB are the same. On node NA, there is no ac signal; on node MB there is an ac signal. If the dc voltages are equal, then the differential later gain stage amplifier 20 will amplify the ac signal and send it to further gain stages.
In operational summary of the example shown in prior art FIG. 2 wherein head 1 of the 6 illustrated heads is selected, when the magnetic resistive head moves to select data at head 1, an ac data signal appears on the resistive portion of the head represented by Rmr1. Transistors Q1 and Q11 amplify this data signal, by the load resistor R1 and the data signal appears at node M. There is no ac signal at node N. The ac data signal at load resistor R1 gets amplified by differential amplifier 20 and is output to further later gain stages. For selecting the read heads, the MOS switch SW1 connects the base of transistor Q1 to capacitor C1. When this occurs, all the current that goes through the load resistor R1 and transistor Q11 goes through transistor Q1. As stated earlier, all the other input transistors Q2-Q6 are not selected as connecting their bases to integrated circuit ground turns them off.
Supply noise is a problem for single ended preamplifier stages as it adversely affects the bit error rate of the preamplifier. That is, if noise is present, the preamplifier may incorrectly send the wrong data through the read channel. Noise may exist in several sources such as the Vcc power supply, ground and substrate. If the noise is not eliminated, it transfers from the first stage into later gain stages of the preamplifier and thus hinders the preamplifier""s Power Supply Rejection (PSR) ability. (Those in the HDD industry use PSR as a rating criteria when choosing a manufacturers preamplifier; a better PSR rating is desirable as it reflects increased ability to eliminate noise from the power supply.)
As an example, as shown in prior art FIG. 2, one source of noise injection is the parasitic capacitance Cp formed by bipolar transistor Q1 collector to substrate capacitance. This parasitic capacitance Cp is illustrated by dotted line connections. If ground noise exists, it can come through this parasitic capacitance Cp and appear at node Y where transistor Q11 and load resistor R1 will amplify it and send it to the signal input node MB of later gain stage differential amplifier 20.
As an example, another source of noise injection is the thermal noise of the scaling resistor 20R1. To help control this noise, the prior art circuit of FIG. 2 adds a capacitor C2 in parallel with the scaling resistor 20R1. The capacitor C2 does not change the transfer function for the serial path of the output read signal; it does not change the gain or bandwidth of the amplifier. This C2 capacitor couples Vcc noise into node N.
The amount of coupling depends upon the frequency of the noise signal. Prior art FIG. 3 is a graph illustrating the amount of noise coupling between the different frequencies of the prior art circuit of FIG. 2. In FIG. 3, the value 0 DB means that if a signal having a reference unit amplitude is input into Vcc, a reference unit of amplitude is output by initial amplification stage 18. As the graph shows, any signal with less than zero DB is attenuated and any signal with DB greater than zero is a gainxe2x80x94it is magnified out. As the frequencies increase, the graph crosses 0 DB and moves upward. The desired frequency band for a HDD is from around 1 megahertz to about 200 megahertz as this is the frequency range at which signals are recorded on the disks. As the figure unfortunately shows, however, the graph crosses 0 DB during this frequency range.
It is thus an object of this invention to improve the PSR ability of a preamplifier. Noise coupled from the power supply, ground, substrate or other sources over the desired frequency range needs to be eliminated so that the data bit error rate of the hard disk drive can be improved.
Other objects and advantages of the invention herein will be apparent to those of ordinary skill in the art having the benefit of the description herein.
The invention herein increases the ability of a single ended initial amplification stage of a preamplifier to eliminate noise over the desired frequency range of about 1 megahertz to about 200 megahertz in hard disk drive applications. The head input transistors are grouped into banks with each bank having separate single ended drive transistors that are multiplexed together. This effectively reduces substrate capacitances of the bipolar NPN head input transistors. In addition, the frequency response of the constant voltage side of the input to the differential amplifier is matched to the frequency response of the signal side of the input to the differential amplifier; that is, the poles of the single ended amplifier are. matched so that the inputs to the differential amplifier are matched. This effectively reduces the ground noise coupled through substrate capacitance of NPN transistors as it becomes common mode to the differential amplifier. In further addition, power supply noise is reduced by pole matching in the input initial amplification stage as the capacitance is doubled on the constant voltage input to the differential amplifier while the resistance is halved on the signal input to the differential amplifier. This matches any Vcc power supply noise on the signal side to that on the constant voltage side of the differential amplifier.